There have been used a variety of data transfer devices which exchange data between elements, such as a display section or a photo-receiving section where signal lines and scanning lines are provided in a matrix pattern, and other elements.
For example, active-matrix substrates used in display devices such as a liquid crystal display device have signal lines for supplying display signals to pixels, and scanning lines for driving a switching element provided for each pixel. In order to drive these signal and scanning lines, external driving circuits (signal line driving circuit, scanning line driving circuit) are installed.
Conventionally, the external driving circuits were provided with the same number of output terminals as the number of signal lines and scanning lines for driving these lines. However, attempts have been made to reduce the number of components of the external circuit and to reduce the cost of installing it, by a method in which the number of ICs is reduced to half or one-third, and signals are supplied selectively by signal line switching elements by branching the ICs. For example, in a method disclosed in Japanese Unexamined Patent Publication No. 234237/1996 (Tokukaihei 8-234237) (published date: Sep. 13, 1996), scanning lines are divided into blocks, and the blocks to which the scanning signals are destined are switched in time so that the scanning lines are sequentially applied to each block by dividing one vertical period with respect to time.
The foregoing conventional structure, however, had a problem that an error occurred on transfer data by the application of a potential on a signal line at a border line while the potential of the signal line is being oscillated by a parasitic capacitance which exists between the signal line and adjacent signal lines.
For example, in the case of a display device, there is a problem that the signal line and pixels which correspond to the border of the blocks are oscillated at the time of switching the blocks by the parasitic capacitance between the signal line and the pixel electrodes. The following explains this principle with reference to a timing chart of FIG. 32, and FIG. 1 which shows a structure according to the present invention. Note that, in reality, there are many other signal lines and their corresponding elements other than those shown in the drawing, which, however, are omitted here for convenience of explanation. The following explanation is based on the case where signals of maximum amplitude are outputted from output lines s1 to s4, which respectively correspond to output terminals of the signal line driving circuit 1, for effecting black display over the entire screen.
Signal lines f′, f, a, and b make up a single block (“first block” hereinafter), and signal lines c, d, e, and e′ makes up another block (“second block” hereinafter). While a scanning line g1 is being selected, a signal is first supplied to the signal lines a and b from the signal line driving circuit 1. The signal is applied to pixels A1 and B2 because the scanning line g1 is selected. Here, no signal is supplied to the signal lines c and d. Then, the signal lines a and b, and the pixels A1 and B1 become on hold, and a signal is supplied to the signal lines c and d from the signal line driving circuit 1, which is then applied to pixels C1 and D1 because the scanning line g1 is selected.
While the scanning line g1 is selected, a signal is sent to control wires SW1 and SW2 subsequently, so as to conduct signal line switching elements (SWa, etc.). First, by selecting SW1, the signal line switching elements SW1 and SW2 are conducted. This allows the signal from the signal line driving circuit 1 to be supplied to the pixels a and b. The signal is applied to the pixels A1 and B1 because the scanning line g1 is selected. Here, no signal is supplied to the signal lines c and d since SW2 is not selected here. Then, SW1 becomes non-selected and SWa and SWb become non-conducted, placing the signal lines a and b and the pixels A1 and B1 on hold. Then, when SW2 is selected and the signal line switching elements SWc and SWd are conducted, the signal from the signal line driving circuit 1 is supplied to the signal lines c and d, which is then applied to the pixels C1 and D1 because the scanning line g1 is selected.
Note that, even though the same signal is supplied to the signal lines a through d in this example of black display over the entire screen, the signal from the signal line driving circuit 1 is normally switched while one scanning line (g1) is selected.
Here, there exists parasitic capacitance Csd between pixel electrodes and signal lines. FIG. 1 only shows Csd at the pixels A1, B1, C1, D1 and pixels A2, B2, C2, D2, there are a number of Csds which equal the number of pixels provided in each signal line, and therefore there are actually capacitance which cannot be ignored compared with the electrostatic capacitance of the entire signal lines. Here, when the destination of the signal is switched from the first block to the second block, i.e., when SW2 is selected while SW1 is non-selected, there occurs polarity inversion of the potential of the signal line s, as shown in FIG. 32. The signal line b is capacitively coupled with the signal line c via the pixel electrodes (plurality of pixels, e.g., B2, in the direction of the signal line c), and since SW1 is non-selected, there is a potential hike of some degree on the signal line b by the polarity inversion of the signal line c. Further, since the scanning line g1 is being selected, the potential hike is supplied to the pixel B1, and the scanning line g1 is switched under this condition.
Because the foregoing operation occurs with respect to all scanning lines, only a single line which corresponds to the signal line b in the display of the entire screen is supplied with a voltage which is higher than that for the other pixels, and as a result the line is recognized as a black line.
The same hike also occurs when SW1 is selected while SW2 is non-selected; however, since the potential is replaced with a correct potential by the selection of SW2 at the next timing, no display problem will be caused with respect to pixel C1. Further, the oscillation due to Csd during non-conduction of the scanning line g1 does not have any difference as an effective value with respect to a display period as a whole, and does not cause any problem.
Even though the foregoing explained the driving over two blocks, for example, in the case of driving over four blocks on the entire screen, there is a problem that a total of three black lines are recognized at the respective borders of the blocks.
This problem is also present in devices other than the display device, for example, such as an X-ray sensor. That is, signal lines and scanning lines are provided in a matrix pattern on a substrate, and a photo-detecting section having a photo-detecting elements is provided thereon. X-rays are detected by the photo-detecting section and converted to an electrical signal, which is then transferred to an external display device, etc., via the signal lines. Even in this case, when signals are transferred by dividing the signal lines into blocks as in the foregoing case, there will be an error on transfer data by the application of a potential on a signal line at the border while the potential of the signal line is being oscillated by a parasitic capacitance which exists between the signal line and adjacent signal lines.